Conventionally, as a semiconductor device of the above type, the technology disclosed in Patent Document 1, for example, is known. In Patent Document 1, as shown in FIG. 1 thereof, onto a lower-tier chip 7 as a support, an upper-tier chip 2 as a semiconductor chip is die-bonded face up. In the semiconductor device 1, the upper chip 2 and passive chip components 3 mounted around the upper chip 2, such as chip capacitors, are connected via wires 5 and a wiring substrate 4, for example.
Patent Document 1: Japanese Unexamined Patent Publication No. 2004-296613
However, as the clock frequency of semiconductor chips (LSI) has increased in recent years, when the wiring distance from the LSI to a capacitor is large, the high frequency impedance due to the wiring is increased. As a result, the noise reduction effect of the capacitor decreases, which may cause the problem that an expected operation of the LSI cannot be obtained at high frequencies.
Accordingly, in the present description, there is provided a semiconductor device in which the wiring distance from a semiconductor chip die-bonded face up to a support to a capacitor is decreased, whereby the noise reduction effect of the capacitor is increased and the reliability of the semiconductor chip during high frequency operation is increased.